Repository Universitas Andalas

Acceleration of Seed Ordering and Selection for High Quality Delay Test

Aisuwarya, Ratna (2012) Acceleration of Seed Ordering and Selection for High Quality Delay Test. Masters thesis, Nara Institute of Science and Technology.

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Seed ordering and selection is a key technique to provide high-test quality with limited resources in Built-In Self Test (BIST) environment. We present a hard-to-detect delay fault selection method to accelerate the computation time in seed ordering and selection processes. This selection method can be used to restrict faults for test generation executed in an early stage in seed ordering and selection processes, and reduce a test pattern count and therefore a computation time. We evaluate the impact of the selection method both in deterministic BIST, where one test pattern is decoded from one seed, and mixed-mode BIST, where one seed is expanded to two or more patterns. The statistical delay quality level (SDQL) is adopted as test quality measure, to represent ability to detect small delay defects (SDDs). Experimental results show that our proposed method can significantly reduce computation time from 28% to 63% and base set seed counts from 21% to 67% while slightly sacrificing test quality.

Item Type: Thesis (Masters)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Unit atau Lembaga: Fakultas Teknologi Informasi > Sistem Komputer
Depositing User: Ms Ratna Aisuwarya
Date Deposited: 21 Jan 2013 06:47
Last Modified: 21 Jan 2013 06:47

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