Aisuwarya, Ratna and Yamato, Yuta and Yoneda, Tomokazu and Inoue, Michiko
(2012)
Acceleration of Seed Ordering and Selection
For High Quality VLSI Delay Test.
In: IPSJ Kansai Branch 2012, September 21, 2012, Osaka, Japan.
Abstract
Seed ordering and selection is a key technique to
provide high-test quality with limited resources in Built-In
Self Test (BIST) environment. We present a hard-to-detect
delay fault selection method to optimize the computation
time in seed ordering and selection processes. This
selection method can be used to select faults for test
generation when it is impractical to target all delay faults
resulting large test pattern count and long Computation
time. Three types of selection categories are considered,
ranged in the number of seeds it produced, which is useful
when we consider computing resources, such as memory
and storage. We also evaluate the impact of the selection
method in mixed-mode BIST when seed are expanded to
more patterns, and evaluate the statistical delay quality
level (SDQL) with the original work. Experimental results
show that our proposed method can significantly reduce
computation time while slightly sacrificing test quality.
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